题目/Title：An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope

作者/Author：
                        Angxiao Yan, Wei Deng, Haikun Jia, Shiyan Sun, Chao Tang, Bufan Zhu, Yu Fu, Hongzhuo Liu, Baoyong Chi

会议/Conference：VLSI Technology and Circuits 2023

地点/Location：Kyoto, Japan

年份/Issue Date：2023.11-16 Jun.

页码/pages：pp.1-2

摘要/Abstract：

This article introduces a digital FMCW PLL with cycle-slipping compensation scheme and wideband digital-to-time converter (DTC) gain calibration to break the limitation of the maximum trackable chirp slope for two-point modulation (TPM) FMCW PLLs. In addition, FM error is minimized by the proposed back-tracking digital-pre-distortion (DPD) scheme. As far as the authors are aware, the proposed FMCW PLL achieves the widest normalized chirp bandwidth and the fastest normalized chirp slope concurrently while retaining decent chirp linearity.