题目/Title：A Low-Voltage Bias-Current-Free Pseudo-Differential Hybrid PLL Using a Time-Interleaving Flip-Flop Phase Detector

作者/Author：
                        Liqun Feng, Qianxian Liao, Woogeun Rhee, Zhihua Wang

会议/Conference：A-SSCC 2023

地点/Location：Haikou, China

年份/Issue Date：2023.05-08 Nov.

页码/pages：pp.1-3

摘要/Abstract：

Low-voltage clock generation is critical for dynamic voltage scaling in modern microprocessors and SoC designs. The performance of several main PLL architectures are limited under low supply voltage as illustrated in Fig. 1. It is difficult for a CP-PLL to maintain good matching with a wide output voltage swing under low supply. In the case of a sub-sampling phase detector (SSPD), the on-resistance of sampling switches is increased, significantly degrading phase noise performance. A digital-intensive PLL architecture would be desirable, but a low-voltage TDC suffers from the substantial variation of time resolution over process and temperature [1]. As a result, a large decoupling capacitor with good supply regulation is required in practice to achieve robust in-band noise performance.