题目/Title：A 20Gbuad NRZ/PAM4 Receiver Frontend in 65nm CMOS

作者/Author：
                        Xin Wu, Ziqiang Wang, Zeliang Zhao, Chun Zhang, Zhihua Wang

会议/Conference：ICSICT 2022

地点/Location：Nangjing, China

年份/Issue Date：2022.25-28 Oct.

页码/pages：pp.1-3

摘要/Abstract：

This paper present a receiver front-end (hereinafter referred to as receiver) that supports NRZ and PAM4 signaling. It includes an analog frontend (AFE) and a decision feedback equalizer (DFE). The AFE consists of a continuous time linear equalizer (CTLE), a variable gain amplifier (VGA) and a buffer. Careful budget is planned to deal with received signal which come through a channel with up to 20dB insertion loss (IL). Several techniques are adopted to improve its bandwidth. The receiver is fabricated in 65nm CMOS process and its core area is 0.34mm 2 . The measurement results show that the receiver could work at 20Gbuad. It draws 167mA from 1V power supply. Finally, the circuit optimizations are discussed according to the experiment.