题目/Title：A Bias-Current-Free Fractional-N Hybrid PLL for Low-Voltage Clock Generation

作者/Author：
                        Xinyu Xu,Zixiang Wan,Woogeun Rhee,Zhihua Wang

期刊/Journal：IEEE Transactions on Circuits and Systems I: Regular Papers

年份/Issue Date：2021Jun.

卷（期）及页码/Volume（No.）&pages：Vol.68, No.9, pp.3611-3620

摘要/Abstract：
This paper describes a bias-current-free fractional-N hybrid phase-locked loop (HPLL) architecture that does not use a charge pump (CP) or a linear time-to-digital converter (TDC). A hybrid loop control with a digital integral path and an analog proportional-gain path offers technology scalability as well as linear phase detection under a low supply voltage. The CP-less analog control path consists of a flip-flop phase detector (PD) and passive loop filters including a programmable notch filter. Unlike the TDC, the flip-flop PD has negligible contribution to the in-band phase noise over different supply voltages. To mitigate ΔΣ quatization noise and PD nonlinearity effects, an FIR-filtered ΔΣ modulation is employed for fractional division. The proposed fractional-N HPLL implemented in 65-nm CMOS operates with a 0.65-V supply except a 0.9-V digital/voltage-controlled oscillator (D/VCO), consuming 1.85 mW at 1.2 GHz. The phase noise of-97 dBc/Hz at 1-MHz offset frequency and the reference spur of-76 dBc with the programmable notch filter are achieved. The measured in-band fractional spur levels vary from-37 dBc to-58 dBc. The experimental results show that the proposed architecture is promising for low-voltage clock generation and modulation systems.