题目/Title：A Low-Spur Current-Biasing-Free Fractional-N Hybrid PLL for Low-Voltage Clock Generation

作者/Author：
                        Xinyu Xu,Woogeun Rhee,Zhihua Wang

会议/Conference：ISCAS 2020

地点/Location：Sevilla, Spain

年份/Issue Date：2020.10-21 Oct.

页码/pages：pp. 1 - 4

摘要/Abstract：
This paper describes a low-voltage fractional-N hybrid phase-locked loop (HPLL) architecture that does not require current biasing. A hybrid loop control with a digital integral path and an analog proportional-gain path offers technology scalability as well as linear phase detection. The analog control path consists of a flip-flop phase detector (PD) and passive loop filters including a programmable notch filter. To mitigate 螖危 quantization noise and PD nonlinearity effects, an FIR-filtered 螖危 modulation is employed for fractional division. The proposed bias-free fractional-N HPLL is implemented in 65nm CMOS. At 1.2GHz output, the phase noise of 鈭?7dBc/Hz at 1MHz offset frequency and the reference spur of 鈭?6dBc with the programmable notch filter are measured. When 14nm FinFET technology is used, simulation results show that a 1.2GHz bias-free PLL can be designed with a 0.4V supply.