题目/Title：一种用于无线收发机的11bit 150MS/s Sub-range SAR ADC IP
                        An 11bit 150MS/s Sub-range SAR ADC IP for Wireless Transceiver

作者/Author：何秀菊,薛春莹,王亚,李福乐,张春,姜学平
                        Xiuju He,Chunying Xue,Ya Wang,Fule Li,Chun Zhang,Xueping Jiang

期刊/Journal：微电子学与计算机 Microelectronics & Computer

年份/Issue Date：2017.May

卷（期）及页码/Volume（No.）&pages：Vol.34, No.5, pp. 1 - 5

摘要/Abstract：
本论文介绍一个用于无线收发机的双通道11bit 150MS/s逐次逼近型（SAR）模数转换器（ADC）。ADC的两通道都采用Sub-range SAR 的结构，电路中使用自举开关采样，提高电路的线性度；采用全动态比较器，以节省功耗；使用基于等效门控环形振荡器的异步高速SAR逻辑，提高ADC的转换速度。此外，在CDAC中采用分裂电容设计以避免使用导通性不良的中间电压连接开关。本设计在Smic55nm Low-Leakage CMOS工艺下流片。IP总面积是0.3 , 核的有效面积是0.046 。测试结果
An 11bit 150MS/s dual-channel successive-approximation-register (SAR) analog-to-digital converter (ADC) IP for wireless transceiver is presented in this paper. Each channel adopts sub-range SAR architecture, which combines bootstrap switches for high linearity, gate-controlled ring oscillator (GCRO) for high speed and dynamic comparator for low power. In addition, division in Capacitive Digital-to-analog Converter (CDAC) avoids capacitors connecting to common-mode voltage (VCM) and the switch transistors incompletely switching on. The 11 bit 150MS/s prototype is fabricated in smic55nm low leakage CMOS process. The active area of dual-channel ADC IP is 0.35 , while the core area is 0.046 . A single channel consumes 2.04mA current and achieves an SNDR of 60.9dB at 150MS/s sample rate and 1.2V supply and reference, resulting in a FOM of 17.9fJ/Conversion-step. Measured DNL and INL are +0.99/–0.81 LSB and +2.21/–1.37 LSB