题目/Title：应用于超宽带收发机的多相时钟生成器的设计
                        A Multiphase Clock Generation for UWB Transceiver

作者/Author：刘小峰,刘铛,李宇根,王志华
                        Xiaofeng Liu,Dang Liu,Woogeun Rhee,Zhihua Wang

期刊/Journal：微电子学与计算机 Microelectronics & Computer

年份/Issue Date：2016.Nov.

卷（期）及页码/Volume（No.）&pages：Vol.33, No.11, pp. 87-90+94

摘要/Abstract：
设计了一款用于超宽带（UWB）收发机的多相位基带时钟生成器。该时钟生成器通过分析锁相环（PLL） 和延时锁定环（DLL）结构的共性，提出了一种全匹配的压控振荡器/压控延时线（VCO/VCDL）双模可配置结 构，使时钟生成器可以分别在 PLL/DLL 两种模式下工作，为 UWB 收发机提供 2GHz 10 相位的基带时钟信号。 该电路基于 TSMC 65 nm CMOS 工艺设计实现，有效面积为 0.03 mm2。根据测试结果，PLL 模式工作时输出相位 噪声为-85.04 dBc/Hz @1 MHz，参考
A multiphase baseband clock generation for UWB transceiver is presented. By combining the similarity of PLL and DLL’s structure, A reconfigurable fully-matched VCO/VCDL with dual mode is proposed. The clock generation system with the proposed VCO/VCDL can work in PLL/DLL mode separately, and provide 10 phase baseband clock signals which is 2GHz. The chip is fabricated in TSMC 65 nm CMOS process, and the active area is only 0.03 mm2 . The testing results show that the output phase noise is -85.04dBc/Hz@1MHz and the reference spur is -46.89dBc in PLL mode. The power consumption of the clock generation is about 2.1 mW under the 1 V supply