题目/Title：用于心电采集的动态调整低功耗24-bit Δ-Σ ADC
                        A Low Power 24-bit Δ-Σ ADC for ECG Signal Acquisition with Dynamic Adjustment

作者/Author：王湾,姜汉钧,徐乃昊,李冬梅,王志华
                        Wan Wang,Hanjun Jiang,Naihao Xu,Dongmei Li,Zhihua Wang

期刊/Journal：微电子学 Microelectronics

年份/Issue Date：2016.Apr.

卷（期）及页码/Volume（No.）&pages：Vol.46, No.2, pp. 150 - 154

摘要/Abstract：
实现了一种用于心电信号采集的动态调整工作模式的低功耗24位Δ-ΣADC。采用3阶5位的调制器结构,高速模式下,SNR达到120.4dB,ENOB为19.71位;低速模式下,SNR为108.4dB,ENOB为17.71位。使用一种自适应的QRS波检测模块,ADC可以根据心电波形实时调整工作模式。针对典型心电信号,采用动态调整模式后的数据量可以压缩至非动态调整时的62.5%,平均功耗可以降低至101.5μW,是非动态调整时的66.7%。
A low-power 24-bit Δ-Σ ADC designed for ECG(electrocardiogram) acquisition with dynamic adjustment is presented. Using a 3rd order 5-bit modulator structure, the ADC can achieve 120.4 dB SNR(Signal-Noise Ratio) and 19.71 bit ENOB in high-speed mode; 108.4 dB SNR and 17.71 bit ENOB in low-speed mode. By adding a QRS detector with dynamic adjustment, the ADC can adjust the working mode according to the wave form of ECG. As to a typical ECG, the amount of data with dynamic adjustment can significantly reduced to 62.5% as compared to the conventional design, while the average power consumption of ADC can be reduced to 101.5 μW, 66.7% of the ADC with no dynamic adjustment.