题目/Title：A 10.3mW 13.6GHz Phase-Locked Loop with Boosted Gm Two-Stage Ring VCO

作者/Author：刘晗,李宇根,王志华
                        Han Liu,Woogeun Rhee,Zhihua Wang

会议/Conference：ICSICT 2016

地点/Location：Hangzhou, China

年份/Issue Date：2016.25-28 Oct.

页码/pages：

摘要/Abstract：
This paper describes an inductorless phase-locked loop (PLL) for 12.8Gb/s (full rate) and 40Gb/s (quad-rate) serial link applications. An integer-N PLL with a very wide bandwidth is implemented in 65nm CMOS, working as a second part of a cascaded PLL system. A gain-boosted two-stage ring oscillator is designed to meet the speed and generate quadrature outputs. The measured tuning range of the proposed ring VCO is 2.2-to-17.2GHz. The PLL consumes 10.3mW from a 1.2V supply at 13.6GHz output. The measured phase noise is -101dBc/Hz at 10MHz offset.