题目/Title：一种基于TSMC 65nm CMOS工艺的3抽头前馈均衡器设计
                        A 3-Tap Feed-Forward-Equalizer in 65nm CMOS

作者/Author：周乃文,多尔泰,王自强,姜汉钧,黄珂
                        Naiwen Zhou,Ertai Duo,Ziqiang Wang,Hanjun Jiang,Ke Huang

期刊/Journal：微电子学 Microelectronics

年份/Issue Date：2015.12

卷（期）及页码/Volume（No.）&pages：pp. 764 - 768

摘要/Abstract：
高速串行接口技术是当前高速数据传输的关键技术之一。前馈均衡器（Feedforward Equalizer，FFE）是高速串行接口中的重要模块电路。本文设计了采用TSMC 65nm CMOS工艺、工作在40Gbps的、用于高速串口发送端的前馈均衡器。文章分析了FFE的抽头数、求和模块、延时模块对均衡效果的影响。电路采用LC网络作为延时单元,并通过设计闭环反馈控制来控制延时时间，解决了高速均衡电路的延时实现问题。电路后仿真结果表明，在40Gb/s数据传输时，该3抽头FFE电路具有20dB的均衡能力，TT—27
High-speed serial interface technology is one of the key technologies in the current high-speed data transmission field. A feed-forward-equalizer (Feed Forward Equalizer, FFE) is an important high-speed serial interface module circuitry. This paper designed a 3-Tap FFE, working in 40Gbps for high-speed serial circuit, in TSMC 65nm CMOS. The tap numbers of FFE, Summer Circuit and Delay Element were analyzed. A delay cell based on LC network, matched impedance, and feedback were used to obtain the lowest power consumption and the best Equalizer performance. The 40Gb/S 3-Tap FFE chip was designed, and post-layout simulation results showed that, at 40 Gb/S input rate, the FFE has a Balance Capacity of 20dB, in TT-27 ℃ craft corner, 1.0V power supply voltage with 51.52mw power.