题目/Title：一种带改进开关和使用新型按比例缩小策略的10位120兆的流水线模数转换器
                        A 10-bit 120-MS/s pipelined ADC with improved switch and layout scaling strategy

作者/Author：周佳,许丽丽,李福乐,王志华
                        Jia Zhou,Lili Xu,Fule Li,Zhihua Wang

期刊/Journal：半导体学报 Journal of Semiconductors

年份/Issue Date：2015

卷（期）及页码/Volume（No.）&pages：Vol.36, No.8

摘要/Abstract：
这篇文章介绍了一种精度为10比特，采样率为120兆的双通道流水线模数转换器(ADC)。这个模数转换器利用了体效应来改善开关的导通性能。在版图绘制中应用了一种新型的按比例缩小的策略。基于0.18μm的CMOS工艺，ADC的整个版图面积为2.05x1.83 mm2。在采样频率为120兆，输入信号频率为4.9兆的情况下，无杂散动态范围达到了74.32dB，信号噪音失真比为55.34dB，3伏供电电压下每通道的功耗为220毫瓦。
A 10 bit, 120 MS/s two-channel pipelined analog-to digital converter (ADC) is presented in this paper. The ADC is featured with improved switch by using body effect to improve its conduction performance. A new scaling down strategy is proposed to get more efficiency in the layout design. Implemented in a 0.18-μm CMOS technology, the ADC’s prototype occupied an area of 2.05x1.83 mm2. With a sampling rate of 120-MS/s and an input of 4.9MHz, the ADC achieves a spurious-free-dynamic range (SFDR) of 74.32 dB and signal-to-noise-and-distortion ratio (SNDR) of 55.34 dB, while consuming 220-mW/channel at 3-V supply.