题目/Title：A 14-bit 200MS/s low-power pipelined flash-SAR ADC

作者/Author：
                        Jifang Wu,Fule Li,Weitao Li,Chun Zhang,Zhihua Wang

会议/Conference：MWSCAS 2015

地点/Location：Fort Collins, CO

年份/Issue Date：2015.2-5 Aug.

页码/pages：pp. 1 - 4

摘要/Abstract：
This paper presents a 14-bit 200MS/s low-power pipelined flash-SAR ADC. A 5-bit front-end without a dedicated sample-and-hold amplifier (SHA) is adopted in the first stage. A 10-bit flash-SAR ADC which is composed of a 3.5-bit flash ADC and a 7-bit asynchronous SAR ADC is used as the second stage, eliminating the need for more pipeline stages. To achieve high performance with power-efficiency, correlated level-shifting (CLS), range-scaling and capacitor sharing techniques are employed. The ADC is designed using a 65nm general purpose (GP) CMOS technology. Post-layout transient simulation results with noise demonstrate that the ADC achieves a SNDR of 71dB and a SFDR of 82dB with an input frequency of 93.19MHz at 200MS/s. The ADC core consumes 25.8mW at a 1.2V supply voltage.