题目/Title：高速JTAG在线调试系统设计
                        Design of High Speed JTAG Interface On-line Debug System

作者/Author：杨诚,张春
                        Cheng Yang,Chun Zhang

期刊/Journal：微电子学 Microelectronics

年份/Issue Date：2014.20 April

卷（期）及页码/Volume（No.）&pages：Vol.44, No.2

摘要/Abstract：
通过分析影响JTAG在线调试系统性能的主要因素，对在线调试系统的设计提出了一种优化方案。优化后的系统设计方案中上位机PC通过USB接口向调试器发出调试命令，由调试器产生JTAG时序实现对芯片的调试和下载功能。另外对芯片内部JTAG调试逻辑的实现过程和片外存储器下载路径进行了优化，提高了调试系统的调试速度和对片外存储器的下载速度。
An optimization design of JTAG on-line debug system was presented through the analysis of the main factors that affected system performance. The host computer PC of the optimization system issued debug commands to the debugger via the USB interface, the debugger generated the JTAG timing to achieve on-chip debug and program download function. In addition，the on-chip JTAG debug logic and off-chip memory download function had been optimized to improve the debugger speed of the system and the download speed of the off-chip memory.