题目/Title：A 1.5GHz all-digital frequency-locked loop with 1-bit ΔΣ frequency detection in 0.18μm CMOS

作者/Author：卓慧莹,李宇,李宇根,王志华
                        Huiying Zhuo,Yu Li,Woogeun Rhee,Zhihua Wang

会议/Conference：VLSI-DAT 2014

地点/Location：Hsinchu

年份/Issue Date：2014.28-30 Apr.

页码/pages：pp. 1 - 4

摘要/Abstract：
A 1.5 GHz all-digital fractional-N frequency-locked loop by utilizing a ΔΣ frequency-to-digital converter (FDC) is implemented in 0.18 μm CMOS. Different from the conventional all-digital phase-locked loop, the all-digital frequency-locked loop (ADFLL) with a 1-bit ΔΣ frequency detector (FD) avoids complex time-to-digital converter (TDC) design and achieves a fine frequency resolution with bi-level oversampled frequency detection, thus enabling low-cost high-frequency synthesis without requiring an advanced CMOS technology. A finite impulse response (FIR) filter is designed to reduce quantization noise from the ΔΣ FDC and provides highly linear loop dynamics in the type-I feedback system. Experimental results show that the proposed ADFLL at 1.4 GHz output achieves a phase noise of -118 dBc/Hz at a 1 MHz offset frequency, consuming 7.3 mW from a 1.8 V supply.