题目/Title：A 2.5GHz ADPLL with PVT-insensitive ΔΣ dithered time-to-digital conversion by utilizing an ADDLL

作者/Author：李延峰,徐妮,李宇根,王志华
                        Yanfeng Li,Ni Xu,Woogeun Rhee,Zhihua Wang

会议/Conference：ISCAS 2014

地点/Location：Melbourne, Australia

年份/Issue Date：2014.1-5 Jun.

页码/pages：pp. 1440 - 1443

摘要/Abstract：
A ΔΣ all-digital delay-locked loop (ADDLL) is proposed to realize a PVT-insensitive time-to-digital converter (TDC) with enhanced linearity in an all-digital phase-locked loop (ADPLL). With the proposed TDC, poor timing resolution and nonlinearity problems are mitigated, enabling a low cost, low comparison frequency TDC design without using the advanced CMOS technology. A novel digitally-controlled delay line (DCDL) is proposed to ensure monotonous and linear mapping between a digital control word and a total time delay. A phase error compensator (PEC) is employed to calibrate periodic phase error of the proposed TDC. A 2.5GHz ADPLL is designed in 0.18m CMOS. Simulation results show that the proposed method effectively reduces fractional spurs caused by the TDC.