题目/Title：A 2.5–4.5 GHz CMOS fast settling PLL for IR-UWB radar applications

作者/Author：
                        Zhicheng Wang,Xican Chen,Yiyu Shen,Woogeun Rhee,Zhihua Wang

会议/Conference：ICSICT 2014

地点/Location：Guilin, China

年份/Issue Date：2014.28-31 Oct.

页码/pages：pp. 1 - 3

摘要/Abstract：
A fully integrated CMOS phase-locked-loop (PLL) frequency synthesizer which generates a four-band hopping carrier for the impulse radio ultra -wideband (IR-UWB) radar transceiver is presented. The proposed PLL can synthesize four frequencies between 2.72 and 4.16 GHz in step of 480 MHz and settles in approximately 100 ns. To achieve fast loop settling, an integer-N architecture that operates with 80-MHz reference frequency and 2-MHz loop bandwidth is implemented. A phase-frequency detector (PFD) with a reset path is proposed for fast settling and a current-configurable charge pump is designed to compensate for the VCO gain nonlinearity. Fabricated in 65 nmCMOS process, the PLL consumes 15 mA from a 1-V supply and achieves the phase noise of -89 dBc/Hz at 10-kHz offset and the spur level of -52 dBc.