题目/Title：一种基于输出码统计的流水线模数转换器数字后台校准算法
                        A digital background calibration algorithm of a pipeline ADC based on output code calculation

作者/Author：邵健健,李玮韬,孙操,李福乐,张春,王志华
                        Jianjian Shao,Weitao Li,Cao Sun,Fule Li,Chun Zhang,Zhihua Wang

期刊/Journal：半导体学报 Chinese Journal of Semiconductors

年份/Issue Date：2012.Nov.

卷（期）及页码/Volume（No.）&pages：Vol.33, No.11, pp. 115010-1-5

摘要/Abstract：
本文提出的是一种基于输出数字码统计的流水线模数转换器数字后台校准算法，该算法不改变级电路的结构，只是需要对转换器的输出码进行统计就可以实现校准的目的。通过分析转换器的输出码，算法可以计算出级电路的权重，从而对输出进行补偿。通过一个实际芯片的验证，转换器的积分非线性从90LSB下降到0.8LSB，微分非线性从2LSB下降到0.3LSB，SNDR从38dB提高到66.5dB，THD从-37dB下降到-80dB，转换器的线性度有很大提高
This paper proposes a digital background calibration algorithm to correct linearity errors in a pipelined analog-to-digital converter (ADC). The algorithm does not modify the analog circuit of pipelined stages and calibrates the raw conversion output by using a backend digital logic. Based on the analysis of the output codes, the calibration logic estimates the bit weight of each stage and corrects the outputs. An experimental 14-bit pipelined ADC is fabricated to verify the algorithm. The results show that INL errors drop from 20 LSB to 1.7 LSB, DNL errors drop from 2 LSB to 0.4 LSB, SNDR grows from 57 to 65.7 dB and THD drops from -58 to -81 dB. The linearity of the pipelined ADC is improved significantly.