题目/Title：A 12-bit, 270MS/s Pipelined ADC with SHA-Eliminating Front End

作者/Author：王烜,杨昌宜,赵晓晓,吴超,李福乐,王志华,吴斌
                        Xuan Wang,Changyi Yang,Xiaoxiao Zhao,Chao Wu,Fule Li,Zhihua Wang,Bin Wu

会议/Conference：ISCAS 2012

地点/Location：Seoul, Korea

年份/Issue Date：2012.20-23 May

页码/pages：pp. 798 – 801

摘要/Abstract：
This paper presents a 12-bit 270MS/s pipelined analog-to-digital converter (ADC) without employing a front-end sample-and-hold amplifier. A novel strategy is established to diminish the aperture error while maintaining both the original tracking time and amplifying time of multiplying digital-to-analog converter (MDAC). It matches the signal paths between comparators and MDAC in the first stage by using proper timing sequence and high-speed dynamic comparators. The measurement results show 63.7dB SNR and 76.1dBc SFDR at 120.1MHz input frequency while the chip’s total power dissipation is 250mW (excluding LVDS drivers) at 1.2V supply. The ADC core occupies 1.7mm2 and is implemented in a 130nm CMOS process.