题目/Title：A 200MS/s 10-bit Current-steering D/A Converter with On-chip Testbench

作者/Author：王少鹏,任彦楠,杨昌宜,李福乐,王志华
                        Shaopeng Wang,Yannan Ren,Changyi Yang,Fule Li,Zhihua Wang

会议/Conference：ICSICT 2010

地点/Location：Shanghai

年份/Issue Date：2010.1-4 Nov.

页码/pages：pp. 296 - 298

摘要/Abstract：
This paper presents a 10-bit 200MS/s CMOS current-steering digital-to-analog converter (DAC) with on-chip testbench. The proposed DAC adapts segmented architecture, composed of 6 MSBs unary and 4 LSBs binary-weighted cells. The measurement results show that the converter achieves a spurious-free dynamic range (SFDR) up to 78.7dBc. The full-scale output current is 20mA with 3V power supply for analog part, while the digital part of the chip operates at 1.8V. The DNL and INL are less than 0.07LSB and 0.15LSB respectively due to an improved current switching scheme. The active area of DAC core is 0.2 mm2 in a standard 1P-6M 0.18μm CMOS process.