题目/Title：Power and jitter optimized VCO design using an on-chip supply noise monitoring circuit

作者/Author：刘宇韬,李宇根,王自强,王志华
                        Yutao Liu,Woogeun Rhee,Ziqiang Wang,Zhihua Wang

会议/Conference：APCCAS 2010

地点/Location：Kuala Lumpur, Malaysia

年份/Issue Date：2010.6-9 Dec.

页码/pages：pp. 939 - 942

摘要/Abstract：
This paper describes a circuit design methodology to optimize both power and jitter performances of the inductorless voltage-controlled oscillators (VCOs) by utilizing an on-chip supplynoise monitoring circuit. As the phase-locked loop (PLL) has a sensitive response to the noise frequency near the loop bandwidth, detecting low frequency tones up to the PLL bandwidth is considered for a supply noise monitoring circuit, which makes it possible to design a low cost semi-digital noise monitoring system. This work affirms the importance of optimizing the voltage swing amplitude of the inductorless VCO, which sets a fundamental trade-off between low power and low noise performances. Transistor level simulations are done to verify the effectiveness of the proposed method for the ring VCO and the relaxation VCO. © 2010 IEEE.