题目/Title：UHF RFID标签基带处理器的低功耗设计
                        Low power Design of an UHF RFID Baseband Processor

作者/Author：王晓晖,张春,马长明,吴行军
                        Xiaohui Wang,Chun Zhang,Changming Ma,Xinjun Wu

期刊/Journal：半导体技术 Semiconductor Technology

年份/Issue Date：2009

卷（期）及页码/Volume（No.）&pages：Vol.34, No.5, pp. 502 - 505

摘要/Abstract：
随着超高频RFID标签的应用越来越广泛，在提高其性能上的需求也越来越迫切。对于无源标签，工作距离是一个非常重要的指标。要提高工作距离，就要降低标签的功耗。本文着重从降低功耗方面阐述了一款基于ISO18000-6 type C协议的UHF RFID标签基带处理器的设计。本文首先简要介绍了设计的结构，继而详细阐述了各种低功耗设计技术，如动态控制时钟频率、寄存器复用、使用计数器和组合逻辑代替移位寄存器、异步计数器、门控时钟等的应用。结果证明，这些措施有效地降低了功耗，仿真结果为在工作电压为1V，时钟为2.5M时
Considering that RFID application is becoming increasingly wider, it is urgent to impove the performance of RFID tag. For passive RFID tag, one of the important specifications is operating distance, which can be extended by reducing the power consumption of tag. This paper presents the digital baseband design of UHF RFID tag based on ISO18000-6(C) protocol and introduces details of some low power design technologies. In the beginning of this paper, RFID application and ISO18000-6(C) protocol are introduced, then the architecture of the design is described. A series of low power design strategies, such as dynamic control of clock, reuse of registers, using counter and combinational logic instead of shift registers, asynchronous counter, clock-gating, etc, are shown in the fourth part. The simulation results indicate that the power of digital baseband processor has been reduced effectively, which is about 4.8μw under 2.5MHz clock frequency with 1.0V power supply. And the chip which implemented the first three strategies consumes 8.03μW under 2.5MHz clock frequency with 1V power supply.