题目/Title：一个高线性13位流水线CMOS A/D转换器
                        A High Linearity,13bit Pipelined CMOS ADC

作者/Author：李福乐,段静波,王志华
                        Fule Li,Jingbo Duan,Zhihua Wang

期刊/Journal：半导体学报 Chinese Journal of Semiconductors

年份/Issue Date：2008.Mar.

卷（期）及页码/Volume（No.）&pages：Vol.29, No.3, pp. 497 - 501

摘要/Abstract：
介绍了一个采用多种电路设计技术来实现高线性13位流水线A/D转换器. 这些设计技术包括采用无源电容误差平均来校准电容失配误差、增益增强(gain-boosting)运放来降低有限增益误差和增益非线性、自举(bootstrapping)开关来减小开关导通电阻的非线性以及抗干扰设计来减弱来自数字供电的噪声.电路采用0.18μm CMOS工艺实现，包括焊盘在内的面积为3.2mm2.在2.5MHz采样时钟和2.4MHz输入信号下测试，得到的微分非线性为-0.18/0.15LSB，积分非线性为-0.35/0.5LS
A 13bit,pipelined analog-to-digital converter (ADC) designed to achieve high linearity is described.The high linearity is realized by using the passive capacitor error-averaging technique to calibrate the capacitor mismatch error,a gain-boosting opamp to minimize the finite gain error and gain nonlinearity,a bootstrapping switch to reduce the switch on-resistor nonlinearity,and an anti-disturb design to reduce the noise from the digital supply.This ADC is implemented in 0.18μm CMOS technology and occupies a die area of 3.2mm2,including pads.Measured performance includes -0.18/0.15LSB of differential nonlinearity,-0.35/0.5LSB of integral nonlinearity,75.7dB of signal-to-noise plus distortion ratio (SNDR) and 90.5 dBc of spurious-free dynamic range (SFDR) for 2.4MHz input at 2.5MS/s.At full speed conversion (5MS/s) and for the same 2.4MHz input,the measured SNDR and SFDR are 73.7dB and 83.9 dBc,respectively.The power dissipation including output pad drivers is 21mW at 2.5MS/s and 34mW at 5MS/s,both at 2.7V supply.