题目/Title：A hybrid spur compensation technique for finite-modulo fractional-N phase-locked loops

作者/Author：
                        Li Zhang,Xueyi Yu,Yuanfeng Sun,Woogeun Rhee,Zhihua Wang,Hongyi Chen,Wang, D.

会议/Conference：A-SSCC 2008

地点/Location：Fukuoka, Japan

年份/Issue Date：2008.3-5 Nov.

页码/pages：pp. 417 - 420

摘要/Abstract：
A finite-modulo fractional-N PLL utilizing a low-bit high-order DeltaSigma modulator is presented. A 4-bit 4th-order DeltaSigma modulator performs deterministic 16-modulo fractional-N operation with less spur generation and negligible quantization noise. Further spur reduction is achieved by charge compensation in the voltage domain and phase interpolation in the time domain, which significantly relaxes the dynamic range requirement of the charge pump compensation current. A 1.8 - 2.6 GHz fractional-N PLL is implemented in 0.18 mum CMOS. The prototype PLL consumes 35.3 mW in which only 2.7 mW is consumed by the digital modulator and compensation circuits.