题目/Title：A Low-Power 12-bit 2GS/s Time-Interleaved Pipelined-SAR ADC in 28nm CMOS Process

作者/Author：
                        Xiao Wang,Chengwei Wang,Fule Li,Zhihua Wang

会议/Conference：ISCAS 2018

地点/Location：Florence, Italy

年份/Issue Date：2018.27-30 May

页码/pages：pp. 1 - 5

摘要/Abstract：
This paper presents a low-power 2-channel 12-bit 2GS/S time-interleaved pipelined-SAR ADC in 28nm CMOS process. The design adopts SHA-less front-end, capacitor sharing between stages, current-reused and ping-pong operated MDAC amplifier, and hybrid reference buffer to reduce power consumption and optimize performance. Pre-layout simulation with noise shows that the proposed ADC achieves SNDR and SFDR of 64.1dB and 69.5dB respectively at Nyquist frequency. The effective resolution bandwidth is extended to 3.2GHz. The ADC consumes only 50mW, in which 30mW is dissipated by the wide-band input buffer. At Nyquist frequency, the proposed ADC achieves a Waiden FOM of 19fJ/conv.-step.