题目/Title：A 0.6V 50-to-145MHz PVT tolerant digital PLL with DCO-dedicated ΔΣ LDO and temperature compensation circuits in 65nm CMOS

作者/Author：
                        Yudong Zhang,Xiaofeng Liu,Woogeun Rhee,Hanjun Jiang,Zhihua Wang

会议/Conference：ISCAS 2017

地点/Location：Baltimore, MD, USA

年份/Issue Date：2017.28-31 May

页码/pages：pp. 1 - 4

摘要/Abstract：
This paper presents an ultra-low voltage and ultra-low power PVT tolerant digital PLL with a semi-digital low dropout regulator (LDO). A low cost integrated temperature compensation circuit (TCC) is proposed and implemented by combining with a proposed 螖危 LDO to reduce temperature variation of the digitally-controlled relaxation oscillator (DCRXO). A 50-to-145MHz PLL implemented in 65nm CMOS consumes a 77.3渭W from a 0.6V supply at 100MHz output and achieves the phase noise of -94.3dBc/Hz at 1MHz offset frequency and the reference spur below -70dBc at 6.25MHz offset frequency. The output frequency variation of open-loop oscillator with the TCC is less than 5% across temperature variation from -20掳C to 90掳C.