题目/Title：
                        An S/H circuit with parasitics optimized for IF-sampling

作者/Author：郑旭强,李福乐,王志军,李玮韬,贾雯,王志华,岳士岗
                        Xuqiang Zheng,Fule Li,Zhijun Wang,Weitao Li,Wen Jia,Zhihua Wang,Shigang Yue

期刊/Journal：半导体学报（英文版） Journal of Semiconductors

年份/Issue Date：2016.June

卷（期）及页码/Volume（No.）&pages：Vol.37, No.6, pp. 065005-1 - 5

摘要/Abstract：

An IF-sampling S/H is presented, which adopts a flip-around structure, bottom-plate sampling technique and improved input bootstrapped switches. To achieve high sampling linearity over a wide input frequency range, the floating well technique is utilized to optimize the input switches. Besides, techniques of transistor load linearization and layout improvement are proposed to further reduce and linearize the parasitic capacitance. The S/H circuit has been fabricated in 0.18- m CMOS process as the front-end of a 14 bit, 250 MS/s pipeline ADC. For 30 MHz input, the measured SFDR/SNDR of the ADC is 94.7 dB/68. 5dB, which can remain over 84.3 dB/65.4 dB for input frequency up to 400 MHz. The ADC presents excellent dynamic performance at high input frequency, which is mainly attributed to the parasitics optimized S/H circuit.