题目/Title：A 80mW 40Gb/s Transmitter with Automatic Serializing Time Window Search and 2-tap Pre-emphasis in 65nm CMOS Technology

作者/Author：黄柯,王自强,郑旭强,张春,王志华
                        Ke Huang,Ziqiang Wang,Xuqiang Zheng,Chun Zhang,Zhihua Wang

期刊/Journal：IEEE Transactions on Circuits and Systems I: Regular Papers

年份/Issue Date：2015May

卷（期）及页码/Volume（No.）&pages：Vol.62, No.5, pp. 1441 - 1450

摘要/Abstract：
This paper presents a 40 Gb/s (38.4-to-46.4 Gb/s) half rate SerDes transmitter with automatic serializing time window search and 2-tap pre-emphasis. By implementing a serializing time window search loop, the serializing timing is guaranteed and circuits running at the highest speed such as latches for retiming and clock tree buffers for delay matching are eliminated. A divider-less sub-harmonically injection-locked PLL (SILPLL) with auto-adjust injection timing is employed to provide low jitter clock source. A power-efficient 2-tap feed-forward equalizer (FFE) based on open loop 1-UI delay generation is implemented as the transmitter equalizer. Fabricated in 65 nm CMOS technology, the transmitter running at 40 Gb/s consumes 80 mW power under 1.2 V supply. The PLL RMS jitter is 98 fs integrating from 100 Hz to 100 MHz and the total jitter of 40 Gb/s eye diagram is 6.7 ps for 1e-12 BER.