题目/Title：A 85mW 14-bit 150MS/s Pipelined ADC with a Merged First and Second MDAC

作者/Author：李玮韬,李福乐,杨昌宜,李盛靖,王志华
                        Weitao Li,Fule Li,Changyi Yang,Shengjing Li, Zhihua Wang

期刊/Journal：China Communications

年份/Issue Date：2015May

卷（期）及页码/Volume（No.）&pages：Vol.12, No.5, pp. 14 - 21

摘要/Abstract：
A low-power 14-bit 150MS/s analog-to-digital converter (ADC) is presented for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multiplying digital-to-analog converter (MDAC) and the second one reduces the total opamp power further. The dedicated sample-and-hold amplifier (SHA) is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the performance. The prototype ADC is fabricated in a 130nm CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 mW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.