题目/Title：A 4×20-Gb/s 0.86pJ/b/lane 2-tap-FFE source-series-terminated transmitter with far-end crosstalk cancellation and divider-less clock generation in 65nm CMOS[C]

作者/Author：袁帅,乌力吉,王自强,郑旭强,贾雯,张春,王志华
                        Shuai Yuan,Liji Wu,Ziqiang Wang,Xuqiang Zheng,Wen Jia,Chun Zhang,Zhihua Wang

会议/Conference：CICC 2015

地点/Location：San Jose, CA, USA

年份/Issue Date：2015.28-30 Sept.

页码/pages：pp. 1 - 4

摘要/Abstract：
A 4×20-Gb/s source-series-terminate (SST) transmitter with 2-tap FFE and far-end crosstalk (FEXT) cancellation is presented. The FFE and crosstalk canceller (XTC) are merged together with the SST driver. The proposed transmitter architecture with divider-less clock generation can not only guarantee the timing requirement for the highest-speed serialization under PVT variation, but also save a lot of hardware cost and power compared with the conventional designs. Fabricated in a 65-nm CMOS technology, the transmitter achieves a maximum data rate of 20-Gb/s with a power efficiency of 0.86pJ/b/lane. For two 2- inch channels with spacing of 30-mil, the measured total jitter (TJ) of the 20-Gb/s eye diagram is 27.8ps for 1e-12 BER, and the peak-to-peak data dependent jitter (DDJ) is improved by 36.9% due to the XTC.