题目/Title：A 9-Gb/s quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology

作者/Author：袁帅,王自强,郑旭强,乌力吉,张春,王志华
                        Shuai Yuan,Ziqiang Wang,Xuqiang Zheng,Liji Wu,Chun Zhang,Zhihua Wang

期刊/Journal：Analog Integrated Circuits & Signal Processing

年份/Issue Date：2014

卷（期）及页码/Volume（No.）&pages：Vol.81, No.3, pp.777 - 788

摘要/Abstract：
A quarter-rate 4-tap decision feedback equalizer (DFE) using new analog sampling and soft-decision technique is proposed in this paper. The proposed DFE introduces two optimizations on basis of the original soft-decision DFE. Firstly, implementation of sample-and-hold (S/H) circuit is changed into the cascade transmission gates to simplify the clock generation. Secondly, 4-tap structure is realized without increasing any hardware complexity to enhance the ability of equalization. To verify the DFE, a simplified transceiver is designed and fabricated in UMC 0.18-μm CMOS process, which mainly consists of a 4-tap DFE, a clock receiver and generator and a 4 to 1 multiplexer (MUX). The measurement results show that the quarter-rate 4-tap DFE can equalize 9Gb/s 27-1 PRBS data passed over a 20cm FR-4 channel with 16.3dB of loss at 4.5GHz and achieve 0.46UI timing margin for bit error rate (BER)=10-12. The active area of the whole transceiver is 0.65 x 0.24mm2, while the DFE occupies 0.13 x 0.18mm2 and draws 7.2mA from 1.8V supply.