题目/Title：A 40Gbps quarter rate CDR using CMOS-style signal alignment strategy in 65nm CMOS

作者/Author：
                        Peng Wang,Xuqiang Zheng,Ziqiang Wang,Chun Zhang,Zhihua Wang

会议/Conference：EDSSC 2014

地点/Location：Chengdu, China

年份/Issue Date：2014.18-20 Jun.

页码/pages：pp. 1 - 2

摘要/Abstract：
This paper presents a 40Gbps quarter rate clock and data recovery (CDR) based on phase interpolator (PI) in 65nm CMOS. Quarter rate architecture is adopted to relax bandwidth requirement. A CMOS-style signal-alignment strategy is proposed to implement 8:32 demultiplexer (Demux) block, achieving 30.9% system power reduction. CDR can track maximum ±488.3ppm frequency offset between transmitter and receiver. Simulation shows that peak-to-peak jitter generation is 827.2fs. CDR consumes 159mW from 1V supply and takes an area of 0.21 mm2.