题目/Title：A 1V, 240 nW, 7 ppm/°C, high PSRR CMOS voltage reference circuit with curvature-compensation

作者/Author：苑朋朋,李冬梅,王鑫,刘立源,张春,王志华
                        Pengpeng Yuan,Dongmei Li,Xin Wang,Li Yuan,Chun Zhang,Zhihua Wang

会议/Conference：ICSICT 2010

地点/Location：Shanghai

年份/Issue Date：2010.1-4 Nov.

页码/pages：pp. 463 - 465

摘要/Abstract：
A low power voltage reference is implemented in a standard 0.18 μm CMOS process. The temperature coefficient (TC) of 7 ppm/°C is achieved in virtue of the output stage which consists of two transistors operating in subthreshold region and saturation region respectively. This kind of output stage is used to adjust the output voltage and compensate the curvature. The line sensitivity is 200 ppm/V in a supply voltage range of 1-3 V, and the power supply rejection ratio (PSSR) is -85 dB and -42 dB at 100 Hz and 10 kHz, respectively. The maximum supply current is 240 nA. The chip area is 0.016 mm2.