题目/Title：An FIR-embedded noise filtering method for ΔΣ fractional-N PLL clock generators

作者/Author：
                        Xueyi Yu,Yuanfeng Sun,Woogeun Rhee,Zhihua Wang

期刊/Journal：IEEE Journal of Solid-State Circuits

年份/Issue Date：2009Sept.

卷（期）及页码/Volume（No.）&pages：Vol.44, No.9, pp. 2426 - 2436

摘要/Abstract：
This paper describes a noise filtering method for ΔΣ fractional- N PLL clock generators to reduce out-of-band phase noise and improve short-term jitter performance. Use of a low-cost ring VCO mandates a wideband PLL design and complicates filtering out high-frequency quantization noise from the ΔΣ modulator. A hybrid finite impulse response (FIR) filtering technique based on a semidigital approach enables low-OSR ΔΣ modulation with robust quantization noise reduction despite circuit mismatch and nonlinearity. A prototype 1-GHz ΔΣ fractional-N PLL is implemented in 0.18 ¿m CMOS. Experimental results show that the proposed semidigital method effectively suppresses the out-of-band quantization noise, resulting in nearly 30% reduction in short-term jitter.