题目/Title：A Fast 1.9 GHz Fractional-N/Integer Frequency Synthesizer with a Self-tuning Algorithm

作者/Author：
                        Shuilong Huang,Zhihua Wang,Huainan Ma

会议/Conference：APCCAS 2006

地点/Location：Singapore

年份/Issue Date：2006.4-7 Dec.

页码/pages：pp. 203 - 206

摘要/Abstract：
A self-tuning, adaptive 1.9GHz fractional-N/integer frequency synthesizer is proposed in the paper. A combined tuning technique of digital tuning and analog tuning is used to decrease the gain of VCO. The adaptive loop is introduced for automatic adjustment of the loop bandwidth. Two operation modes (fractional-N/integer) are achieved by switching on/off the output signal of SigmaDelta modulator. Just a programmable counter is needed for the swallow pulse divider. Based on 0.18 mum 1.8V CMOS technology. Simulation shows that the frequency synthesizer has a 100 KHz loop bandwidth, a <15mus settling time, and the phase noise is lower than -123dBc@ 600 KHz